This invention relates to a system for checking control data integrity in the switching element of a high speed packet switching network node and more particularly to checking control data integrity during hardware-based multicast switching operations.
Modem digital networks are made to operate in a multimedia environment and interconnect a very large number of users and applications through fairly complex digital communication facilities.
FIG. 1 shows an example of the complexity of present networks. Represented is a backbone network (100), e.g. an Asynchronous Transfer Mode (ATM) network, with multiple end users attached to the network. Some users are directly attached to the ATM network. Others are attached to the ATM network via an access network (102).
As represented in FIG. 1, the system operates in a multimedia environment by transporting pure data as well as video and audio information, the latter possibly being provided by telephone users attached through a private branch exchange (PBX) or central exchange (CX) (103), as well as being provided by base stations (not shown) relaying voice data provided by mobile telephone stations via so-called mobile switch centers (not shown).
Due to the variety of users"" profiles and distributed applications, network traffic is becoming more and more bandwidth-consuming, non-deterministic and requiring more connectivity.
This has been the driver for the emergence of fast packet switching network architectures in which data, voice and video information are digitally encoded and then segmented into fixed (in ATM mode of operation) or variable length (in so-called packet transfer mode or PTM mode of operation) packets. In ATM networks, the fixed length packets are normally referred to as xe2x80x9ccellsxe2x80x9d with each cell including 48 data bytes plus a 5-bytes long header, as defined by the CCITT standardization Group/ITU. The packets are then transmitted through a common set of nodes (106, 107, . . . , 113) and links or trunks, interconnecting the nodes to constitute the network communication facilities as represented in FIG. 1.
In ATM networks, regardless of the format of original packets, each packet is converted into fixed length cells for switching operations within each network node.
The need for efficient transport of mixed traffic streams in networks implementing these new architectures imposes a set of performance and resource requirements including very high throughput, short packet processing time, flexibility to support a wide range of connectivity options and efficient flow and congestion control. Congestion is a network state in which the network performance degrades due to saturation of network resources such as communication links bandwidth, and more particularly processor cycles or memory buffers located within the nodes.
One of the key requirements for high speed packet switching networks is to reduce the end to end delay in order to satisfy real time delivery constraints when required and to achieve the necessary high nodal throughput for the transport of voice and video.
Increases in link speeds have not been matched by proportionate increases in the processing speeds of communication nodes and this may induce a serious limitation on network node operating power. The fundamental challenge for high speed networks is to minimize the processing time and to take full advantage of the high speed/low error rate technologies. Most of the transport and control functions provided by the new network architectures are performed on an end to end basis. But the number of operations to be performed per time unit still remains particularly high.
One basic advantage of packet switching techniques (as opposed to so-called circuit switching techniques) is that different types of data can be statistically multiplexed over the same line, which optimizes utilization of the transmission bandwidth. A drawback, however, is that successive packets may require different amounts of time to travel from source to destination. Delays between receipt of successive packets or jitter (variations in packet-to-packet delays) can be detrimental for transmission of isochronous data, like video or voice. This is why methods have been proposed to control networks in such a way that delays and jitters are limited (bound) for every new connection that is set up across a packet switching network.
Different types of data traffic need to be treated differently in order to make sure the data is usable at its destination. Distinctions are made among various types of traffic through assignment of different specific priorities. In other words, when a source terminal requests a connection to a destination terminal via the network, a particular quality of service (QoS) is specified in terms of maximum allowable delay (T_max) and packet loss probability (P_loss) based on the nature of the traffic provided by the source.
As is already known in the art of digital communication, and is disclosed in several U.S. Patents (U.S. Pat. Nos. 6,118,791, 6,055,235 and 6,324,164), a network node can include input and output adapters interconnected by a so-called node switch. Each adapter includes series of buffers or shift registers where transiting packets are temporarily stored. An important requirement for any network node is that it should be able to switch and and transmit data at basically the same rate at which the data arrives. For a 1 Gigabit per second (1 Gpbs) link, that means the node must receive, switch and transmit a cell every 0.43 microsecond.
Also to be taken into consideration is the fact that the data flow is along paths called xe2x80x9cVirtual Channelsxe2x80x9d (VC) and xe2x80x9cVirtual Pathsxe2x80x9d (a VP representing a group of VCs) carried within the physical links or lines. Each virtual path or virtual channel is set up as a series of pointers through the network. A cell header contains identifiers such as xe2x80x9cVirtual Path Identifiersxe2x80x9d (VPI) and xe2x80x9cVirtual Channel Identifiersxe2x80x9d (VCI), identifying the connection assigned to the cell, enabling the network switch element to route the cell toward its final destination. Cells on a particular Virtual Channel always follow the same path through the network and are delivered to the destination in the order in which they are received. Once a connection is set up, a Virtual Channel Connection is defined from source user to destination user.
Along with the emerging types of data communication traffic (e.g., multimedia, video distribution/conferencing), there is a need for a system to be capable of handling so-called multipoint connections; that is, a need to be able to send the same cell to different end-users. Cells directed to multiple end-users are called xe2x80x9cmulticastxe2x80x9d or xe2x80x9cbroadcastxe2x80x9d cells. A significant difference between multicasting and broadcasting is defined later in this description. Generally, the source transmitting a multicast cell does not possess necessary information relating to the multiple destinations for said cell and the multicast function must be provided through the network nodes. It is then mandatory for the switch nodes to be able to perform such multicast function. A significant fact is that cell multicast operations require the use of correlative control data which must be simultaneously sent to sets of devices where the set membership may change from one time to the next. The need for simultaneous distribution imposes timing challenges. This requirement is taken into account in various switch implementations. A typical implementation is the so-called shared buffer approach.
While integrity checking of multicasted data is clearly desirable, such checking should not interfere with normal operation of the network node and more particularly should not affect node performance.
The present invention is a system for checking data transfer integrity in a switching element of the type in which multicasting is performed by simultaneously switching data from a first register to registers in a set of device registers. The set of device registers includes all possible multicast destinations in the switching element. For a particular multicast operation, certain registers in the set are selected via a set of select lines from a select circuit in the switching element. The outputs from the device registers are connected to a logic OR gate circuit, the output of which is connected to an input to the first register. The system further includes a compare circuit which receives outputs from the individual device registers and from the select lines from the select circuit. Data transfer integrity is performed using the outputs from the compare circuit.